Electronic circuit boards in high technology applications have reached a point where testing the circuit board for continuity problems is not cost effective and often not possible. Traditional methods of testing circuit boards consisted of probing the integrated circuit input and output pins and selected points on the circuit board with test probes. The combination of surface mount technology and miniaturization of components has reduced or eliminated the physical space available for probe testing. Further, the reduced width of conductor traces on modern circuit boards makes probe testing even more difficult.
To overcome the problems encountered with probe testing, manufacturers have two testing techniques available. The first technique requires an actual functional test of the circuit board. This option is both time consuming and expensive. Functional testing is often not practical on the circuit board level and may have to be conducted on a system level, where the system may incorporate a large number of circuit boards. It can be seen that using this technique it can be difficult to isolate the cause of a faulty circuit.
The second testing technique involves the use of a test procedure such as boundary scan testing where test elements are built into the IC's populated on the circuit board. Boundary scan testing offers access to the input and output pins of the IC's on the printed circuit board by means of a test bus connecting the test elements. Boundary scan testing can provide an effective means for both board level and system-level testing. Because boundary scan technology is incorporated into the IC's, circuit boards can be built which are not testable using traditional probe testing technology.
Boundary scan testing involves a number of boundary scan cells inside each IC corresponding to each IC input and output pin so that signals at the IC's boundaries can be controlled and observed. Provisions, therefore, have to be made at the component level (IC) in order to use boundary scan testing at a system level.
Standard boundary scan testing techniques provide a means for testing both the connections between integrated circuits and the core logic of the integrated circuit. By using the boundary scan cells in the IC to isolate the IC from the rest of the circuit board, a test signal can be applied to the inputs of the IC and the outputs from the IC can be captured by the boundary scan cell associated with the output. The core logic of a given IC can therefore be tested. This test procedure can be conducted using a slow speed static test signal. A good description of a standard boundary scan test can be found in "The ABCs of Boundary-Scan Test", John Fluke Mfg. Co., 1991.
Boundary scan testing also provides a means for testing the connections between components on the circuit board. This is performed by applying a status test signal to the output of an IC, using the boundary scan cell associated therewith, and capturing the signal using the boundary scan cell associated with an input of another IC. This test technique is effective for testing the continuity between components after the circuit board has been populated. Because interconnect testing is conducted in a static condition, standard boundary scan testing does not provide a means for testing the circuit board connections in a simulated operational state. That is, the characteristics of a given connection between components on a printed circuit board cannot be tested under an operational clocked condition.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a boundary scan test which can test and profile the connection between components in an operational clocked condition.